SOUNDBITE【PDF 50/68 页】BOARD DEMO AUDIO DEVELOPMENT

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Enhanced Serial Audio Interface Timing

Table 22. Enhanced Serial Audio Interface Timing (continued)

No.

Characteristics 1, 2, 3

Symbol

Expression

Min

Max

Condition 4

Unit

88 SCKT edge to transmitter #0 drive enable

—

—

—

34.0

x ck

ns

deassertion 7

—

20.0

i ck

89 FST input (bl, wr) setup time before SCKT

—

—

2.0

—

x ck

ns

edge 6

21.0

—

i ck

90 FST input (wl) setup time before SCKT edge

—

—

2.0

—

x ck

ns

21.0

—

i ck

91 FST input hold time after SCKT edge

—

—

4.0

—

x ck

ns

0.0

—

i ck

92 FST input (wl) to data out enable from high

—

—

—

27.0

—

ns

impedance

93 FST input (wl) to transmitter #0 drive enable

—

—

—

31.0

—

ns

assertion

94 Flag output valid after SCKT edge

—

—

—

32.0

x ck

ns

—

18.0

i ck

95 HCKR/HCKT clock cycle

96 HCKT input edge to SCKT output

97 HCKR input edge to SCKR output

—

—

—

2 x T C

—

—

13.4

—

—

—

18.0

18.0

ns

ns

ns

Note:

1. V CORE_VDD = 1.25 ± 0.05 V; T J = –40°C to 115°C for 150 MHz; T J = 0°C to 100°C for 181 MHz; C L = 50 pF

2. SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

3. bl = bit length

wl = word length

wr = word length relative

4. i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that SCKT and SCKR are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that SCKT and SCKR are the same clock)

5. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal

waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit

clock of the first word in frame.

7. Periodically sampled and not 100% tested

8. ESAI_1 specs match those of ESAI_0

DSP56371 Data Sheet, Rev. 4.1

50

Freescale Semiconductor

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